Logic Synthesis and Verification Algorithms by Fabio Somenzi, Gary D. Hachtel

Logic Synthesis and Verification Algorithms

Fabio Somenzi, Gary D. Hachtel

564 pages missing pub info (editions)

nonfiction computer science design science informative slow-paced
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Description

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation ...

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