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564 pages • missing pub info (editions)
ISBN/UID: 9781475770360
Format: Paperback
Language: English
Publisher: Springer
Publication date: 18 March 2013
Description
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation ...
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564 pages • missing pub info (editions)
ISBN/UID: 9781475770360
Format: Paperback
Language: English
Publisher: Springer
Publication date: 18 March 2013
Description
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation ...
Community Reviews
Content Warnings